(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a metal oxide semiconductor field effect transistor, (MOSFET), device, in which the source/drain region of the MOSFET device, is isolated from the semiconductor substrate, by a thin silicon oxide layer.
(2) Description of the Prior Art
The semiconductor industry is continually striving to improve the performance of devices, via use of micro-miniaturization, or the use of sub-micron features. The objective of micro-miniaturization has been successfully addressed via advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use more sensitive photoresist masking materials, have allowed sub-micron images to be routinely achieved in masking photoresist layers. In addition the development of advanced dry etching tools, and procedures, have allowed the sub-micron images in photoresist masking layers, to be successfully transferred to underlying materials, used for the fabrication of sub-micron MOSFET devices. These sub-micron, MOSFET features, such as the sub-micron channel length, located under narrow gate structures, between source/drain regions, allow increased MOSFET performance to be achieved. In addition the smaller MOSFET features, achieved via fabrication enhancements, result in capacitance decreases, such as a decreased source/drain to substrate capacitance, achieved via smaller source/drain features, thus also resulting in improvement of MOSFET device performance.
In addition to MOSFET performance enhancements, achieved via micro-miniaturization, and the accompanying reductions in performance degrading capacitance, additional capacitance decreases, or performance enhancements can be achieved via structural enhancements. The use of a silicon on insulator, (SOI), technology, allowing the MOSFET device to be fabricated on a SOI layer results in capacitance decreases between the semiconductor substrate, and overlying, interfacing regions of the MOSFET device. For example Chan et al. in U.S. Pat No. 5,610,083, teach a procedure for fabricating a MOSFET device on a SOI layer, and thus achieve performance enhancements, when compared to counterparts, where the MOSFET device was formed directly on a semiconductor substrate. However the use of special semiconductor substrates, needed for the SOI technology, is expensive, and although performance objectives may be satisfied using a SOI wafer, the as important cost objectives, are not satisfied.
This invention will describe a procedure for obtaining a MOSFET in which an insulator layer is formed only between heavily doped source/drain regions and the semiconductor substrate. The use of this insulator layer, or the pseudo SOI layer, results in capacitance reductions, performance enhancements, via removal of the source/drain to substrate interface, while maintaining cost, via use of a conventional semiconductor substrate.
It is an object of this invention to improve the performance of a MOSFET device, by minimizing junction capacitance.
It is another object of this invention to fabricate a MOSFET device, using a thin insulator layer only between heavily doped/source drain regions, and the semiconductor substrate.
In accordance with the present invention a method for fabricating a MOSFET device, using an insulator layer between a heavily doped source/drain region, and the semiconductor substrate, used to decrease junction capacitance, is described. A gate insulator layer is thermally grown on regions of a semiconductor substrate, between isolation regions. A polysilicon gate structure, with an overlying insulator hard mask, is formed on the gate insulator layer. A lightly doped source/drain is formed in the region of the semiconductor substrate, not covered by the polysilicon gate structure, followed by the creation of insulator spacers, on the sides of the polysilicon gate structure. An anisotropic, reactive ion etching, (RIE), procedure is employed to remove regions of the semiconductor substrate, not covered by the polysilicon gate structure, not covered by the insulator spacers, and not covered by the isolation regions, resulting in openings in the semiconductor substrate, between the insulator spacers, on the polysilicon gate structure, and the isolation regions, and also resulting in a segment of the lightly doped source and drain region, underlying the insulator spacer. A thin insulator layer is next thermally grown on the exposed surfaces of the opening in the semiconductor substrate. A first silicon deposition, and etch back, is performed to refill the opening in the semiconductor substrate, to a level approximately equal to the bottom of the lightly doped source/drain segment. The thin insulator layer, on the sides of the lightly doped source/drain segment is next removed, followed by a second silicon deposition, and etch back, completely filling the opening in the semiconductor substrate. A heavily doped source/drain region is then formed in the silicon fill, in the opening in the semiconductor substrate, with the heavily doped source/drain region interfacing the region of the lightly doped source/drain segment, located under the insulator spacer, and with the reemainder of the heavily doped source/drain region residing on the thin insulator layer, in the region in which the thin insulator layer overlays the sides of the opening in the semiconductor substrate.